In this paper, design of 32-bit parallel multiplier is presented, by introducing Carry Save Adder (CSA) in partial product lines. The multiplier given in this paper is modeled using VHDL (Very ...

In this paper VHDL implementation of 8-bit Arithmetic Logic Unit (ALU) is presented. The design was implemented using VHDL Xilinx Synthesis tool ISE 13.1 and targeted for Spartan device.